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W19B320AT/B
SA = Address of the sector to be verified (in AUTOSELECT mode) or erased. Address bits A20-A12 uniquely select any sector.
BA = Address of the bank that is being switched to AUTOSELECT mode, is in bypass mode, or is being erased
Notes:
1. See Bus Operations Table for details.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the AUTOSELECT command sequence, all bus cycles are write cycles.
4. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A20-A11 are “don’t care”.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the AUTOSELECT mode, or if DQ5 goes high (while the bank is providing status
information).
8. The fourth cycle of the AUTOSELECT command sequence is a read cycle. The system must provide the bank address
to obtain the manufacturer ID, device ID, or Security Sector factory protect information. Data bits DQ15-DQ8 are don’t
care. See the AUTOSELECT Command Sequence section for more information.
9. The data is 82h for factory locked and 02h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or enter the AUTOSELECT mode, when in the Erase
Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank
address.
14. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address.
15. Command is valid when device is ready to read array data or when device is in AUTOSELECT mode.
7.5.5
Write Operation Status
STATUS
DQ7
(NOTE 2)
DQ6
DQ5
(NOTE1)
DQ3
DQ2
(NOTE 2)
RY/#BY
Standard
Mode
Embedded Program
Algorithm
Embedded Erase Algorithm
#DQ7
0
Toggle
Toggle
0
0
N/A
1
No toggle
Toggle
0
0
Erase
Erase
Suspend
Mode
Erase-
Suspend
Read
Suspended
Sector
Non-Erase
Suspended
Sector
1
Data
No toggle
Data
0
Data
N/A
Data
Toggle
Data
1
1
Erase-Suspend-Program
#DQ7
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to DQ5 description section for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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功能描述:IC FLASH 32MBIT 70NS 48TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 产品变化通告:Product Discontinuation 26/Apr/2010 标准包装:136 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步，DDR II 存储容量:18M（1M x 18） 速度:200MHz 接口:并联 电源电压:1.7 V ~ 1.9 V 工作温度:0°C ~ 70°C 封装/外壳:165-TBGA 供应商设备封装:165-CABGA（13x15） 包装:托盘 其它名称:71P71804S200BQ